Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip
Journal of Electronic Testing: Theory and Applications
Constraint extraction for pseudo-functional scan-based delay testing
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Functional constraints vs. test compression in scan-based delay testing
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Functional Constraints vs. Test Compression in Scan-Based Delay Testing
Journal of Electronic Testing: Theory and Applications
Conflict driven scan chain configuration for high transition fault coverage and low test power
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
A novel test application scheme for high transition fault coverage and low test cost
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
| Hi-index | 0.00 |
A structurally testable delay fault might become untestable inthe functional mode of the circuit due to logic or timing constraints or both. Experimental data suggests that there couldbe a large difference in the number of structurally and functionally testable delay faults. However, this difference is usually calculated based only on logic constraints. It is unclearhow this difference would change if timing constraints weretaken into consideration, especially when using statistical timing models. In this paper, our goal is to better understandhow structural and functional test strategies might affect thedelay test quality and consequently, change our perception ofthe delay test results.