Delay Test Scan Flip-Flop: DFT for High Coverage Delay Testing

Authors:
Gefu Xu;Adit D. Singh
Affiliations:
Auburn University, AL;Auburn University, AL
Venue:
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Year:
2007

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Abstract

Scan based delay testing is currently mostly implemented using launch-on-capture (LOC) delay tests. Launch-on-shift (LOS) tests are generally more effective, achieving higher fault coverage with significantly fewer test vectors, but require a fast scan enable, which is not supported by most designs. We present a low cost solution for implementing LOS tests by adding a small amount of logic (six transistors) in each flip-flop to align the slow scan enable signal to the clock edge. Our new design can support full LOS and LOC testing, achieving an average TDF coverage of 92.67% in this combined mode for the ISCAS89 benchmarks. Adding a second slow global scan enable signal also allows mixed LOC/LOS tests, which can further increase coverage up to 94.86% on average for ISCAS89 benchmarks.