At-speed delay testing of synchronous sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Too much delay fault coverage is a bad thing
Proceedings of the IEEE International Test Conference 2001
X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction
ITC '02 Proceedings of the 2002 IEEE International Test Conference
High-Frequency, At-Speed Scan Testing
IEEE Design & Test
IEEE Transactions on Computers
Efficient techniques for transition testing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Tri-Scan: A Novel DFT Technique for CMOS Path Delay Fault Testing
ITC '04 Proceedings of the International Test Conference on International Test Conference
Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction
IEEE Transactions on Computers
Delay Test Scan Flip-Flop: DFT for High Coverage Delay Testing
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Functional Constraints vs. Test Compression in Scan-Based Delay Testing
Journal of Electronic Testing: Theory and Applications
ATS '07 Proceedings of the 16th Asian Test Symposium
Layout-aware scan chain reorder for launch-off-shift transition test coverage
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Critical Path Selection for Delay Test Considering Coupling Noise
ETS '08 Proceedings of the 2008 13th European Test Symposium
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
Low-power scan testing for test data compression using a routing-driven scan architecture
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power supply noise reduction for at-speed scan testing in linear-decompression environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A novel test application scheme for high transition fault coverage and low test cost
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
On path delay testing in a standard scan environment
ITC'94 Proceedings of the 1994 international conference on Test
Test data compression using selective encoding of scan slices
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
MVP: capture-power reduction with minimum-violations partitioning for delay testing
Proceedings of the International Conference on Computer-Aided Design
X-compact: an efficient response compaction technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test compaction for small-delay defects using an effective path selection scheme
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Test data compression is a much more difficult problem for launch-on-capture (LOC) delay testing, because test data for LOC delay testing is much more than that of stuck-at fault testing, and LOC delay fault test generation in the two-frame circuit model can specify many more inputs. A new scan architecture is proposed to compress test stimulus data, compact test responses, and reduce test application time for LOC delay fault testing. The new scan architecture merges a number of scan flip-flops into the same group, where all scan flip-flops in the same group are assigned the same values for all test pairs. Sufficient conditions are presented for including any pair of scan flip-flops into the same group for LOC transition, non-robust path delay, and robust path delay fault testing. Test data for LOC delay testing based on the new scan architecture can be compressed significantly. Test application time can also be reduced greatly. Sufficient conditions are presented to construct a test response compactor for LOC transition, non-robust, and robust path delay fault testing. Folded scan forest and test response compactor are constructed for further test data compression. Sufficient experimental results are presented to show the effectiveness of the method.