All digital built-in delay and crosstalk measurement for on-chip buses
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Temperature effect on delay for low voltage applications
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the IEEE International Test Conference 2001
Correlations between path delays and the accuracy of performance prediction
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Achieving At-Speed Structural Test
IEEE Design & Test
Speed Binning with Path Delay Test in 150-nm Technology
IEEE Design & Test
Variations-aware low-power design with voltage scaling
Proceedings of the 42nd annual Design Automation Conference
Variation-tolerant circuits: circuit solutions and techniques
Proceedings of the 42nd annual Design Automation Conference
On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design
ITC '04 Proceedings of the International Test Conference on International Test Conference
A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
An on-chip NBTI sensor for measuring PMOS threshold voltage degradation
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Within-Die Variation-Aware Scheduling in Superscalar Processors for Improved Throughput
IEEE Transactions on Computers
Temperature- and Voltage-Aware Timing Analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
| Hi-index | 0.00 |
Maximum operating frequency (Fmax) of a system often needs to be determined at multiple operating points, defined by voltage and temperatures. Such calibration is important for the speed binning process, where the voltage-frequency (V-Fmax) relation needs to be accurately determined to sort chips into different bins that can be used for different applications. Moreover, adaptive systems typically require Fmax calibration at multiple operating points in order to dynamically change operating condition such as supply voltage or body bias for power, temperature, or throughput management. For example, a Dynamic Voltage and Frequency Scaling (DVFS) system requires accurate delay calibration at multiple operating voltages in order to apply the correct operating frequency corresponding to a scaled supply. In this article, we propose a low-overhead design technique that allows efficient characterization of Fmax at different operating voltages and temperatures. The proposed method selects a set of representative timing paths in a circuit based on their temperature and voltage sensitivities and dynamically configures them into a ring oscillator to compute the critical path delay. Compared to existing Fmax calibration approaches, the proposed approach provides the following two main advantages: (1) it introduces a delay sensitivity metric to isolate few representative timing paths; (2) it considers actual timing paths instead of critical path replicas, thereby accounting for local within-die delay variations. The all-digital calibration method is robust under process variations and achieves high delay estimation accuracy ( 4% error) at the cost of negligible design overhead (1.7% in delay, 0.3% in power, and 3.5% in die-area).