Process variation characterization of chip-level multiprocessors
Proceedings of the 46th Annual Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
VAIL: variation-aware issue logic and performance binning for processor yield and profit improvement
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Performance-asymmetry-aware scheduling for Chip Multiprocessors with static core coupling
Journal of Systems Architecture: the EUROMICRO Journal
Low-power resource binding by postsilicon customization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hi-index | 14.98 |
Within-die parameter variations can cause wide delay distribution among similar functional units in superscalar processors. Conventionally, the frequency of operation is reduced to accommodate the slowest unit, which in turn degrades throughput. We present a low-overhead design technique that sets the operating frequency in a superscalar processor based on the faster units, and allows more cycles for the slower units. We propose an associated priority scheduling strategy to schedule instructions in the functional units to maximize throughput. Simulation results on a set of benchmarks show that by assigning a higher scheduling priority to faster units, we can achieve 18% improvement in performance on average with negligible design overhead.