Fast Methods to Estimate Clock Jitter due to Power Supply Noise*This paper was presented at Karuizawa Workshop.

Authors:
Koutaro Hachiya;Takayuki Ohshima;Hidenari Nakashima;Masaaki Soda;Satoshi Goto
Affiliations:
The authors are with NEC Electronics Corp., Kawasaki-shi, 211-8668 Japan. E-mail: k.hachiya@ieee.org,;The authors are with NEC Electronics Corp., Kawasaki-shi, 211-8668 Japan. E-mail: k.hachiya@ieee.org,;The authors are with NEC Electronics Corp., Kawasaki-shi, 211-8668 Japan. E-mail: k.hachiya@ieee.org,;The authors are with NEC Electronics Corp., Kawasaki-shi, 211-8668 Japan. E-mail: k.hachiya@ieee.org,;The author is with the Graduate School of Information, Production and Systems, Waseda University, Kitakyushu-shi, 808-0135 Japan.
Venue:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Year:
2007

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ACM Transactions on Design Automation of Electronic Systems (TODAES)

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Abstract

In this paper, we propose two methods to estimate clock jitter caused by power supply noise in a LSI (Large-Scale Integrated circuit). One of the methods enables estimation of clock jitter at the initial design stage before floor-planning. The other method reduces simulation time of clock distribution network to analyze clock jitter at the design verification stage after place-and-route of the chip. For an example design, the relative difference between clock jitter estimated at the initial design stage and that of the design verification stage is 23%. The example result also shows that the proposed method for the verification stage is about 24 times faster than the conventional one to analyze clock jitter.