A synthesizable, fast and high-resolution timing measurement device using a component-invariant vernier delay line

Embedded Timing Analysis: A SoC Infrastructure

IEEE Design & Test

Investigations for Minimum Invasion Digital Only Built-In “Ramp” Based Test Techniques for Charge Pump PLL's

Journal of Electronic Testing: Theory and Applications

Random Jitter Extraction Technique in a Multi-Gigahertz Signal

Proceedings of the conference on Design, automation and test in Europe - Volume 1

A Scalable On-Chip Jitter Extraction Technique

VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium

Jitter spectral extraction for multi-gigahertz signal

Proceedings of the 2004 Asia and South Pacific Design Automation Conference

On-Chip Digital Jitter Measurement, from Megahertz to Gigahertz

IEEE Design & Test

Detection and Evaluation of Deterministic Jitter Causes in CP-PLL's Due to Macro Level Faults and Pre-Detection Using Simple Methods

Journal of Electronic Testing: Theory and Applications

A Low-Cost Jitter Measurement Technique for BIST Applications

Journal of Electronic Testing: Theory and Applications

On-Chip Random Jitter Testing Using Low Tap-Count Coarse Delay Lines

Journal of Electronic Testing: Theory and Applications

Path-RO: a novel on-chip critical path delay measurement under process variations

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design

Self-Measurement of Combinatorial Circuit Delays in FPGAs

ACM Transactions on Reconfigurable Technology and Systems (TRETS)

System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability

Low-overhead Fmax calibration at multiple operating points using delay-sensitivity-based path selection

ACM Transactions on Design Automation of Electronic Systems (TODAES)

On-Chip Delay Measurement Based Response Analysis for Timing Characterization

Journal of Electronic Testing: Theory and Applications

Design and analysis of a delay sensor applicable to process/environmental variations and aging measurements

IEEE Transactions on Very Large Scale Integration (VLSI) Systems