Embedded Timing Analysis: A SoC Infrastructure
IEEE Design & Test
Proceedings of the IEEE International Test Conference 2001
Architecting Millisecond Test Solutions for Wireless Phone RFIC's
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A Method for Measuring the Cycle-to-Cycle Period Jitter of High-Frequency Clock Signals
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
An On-Chip Short-Time Interval Measurement Technique for Testing High-Speed Communication Links
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
BIST for Phase-Locked Loops in Digital Applications
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Noise-Insensitive Digital BIST for any PLL or DLL
Journal of Electronic Testing: Theory and Applications
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Design specification for BER analysis methods using built-in jitter measurements
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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One of the challenges of testing at multiGbps rates is jitter characterization. This article introduces a new technique that allows for attaining on-chip measurements at a substantial level of accuracy. The authors propose new algorithms that allow a wide frequency range, supporting the desired accuracy while guaranteeing signal integrity and low overhead.