An On-Chip Short-Time Interval Measurement Technique for Testing High-Speed Communication Links

Authors:
Jiun-Lang Huang;Kwang-Ting Cheng
Affiliations:
-;-
Venue:
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Year:
2001

Citing 0
Cited 5

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On-chip short-time interval measurement system for high-speed signal timing characterization

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Abstract

In this paper, we present a BIST scheme for on-chip short-time interval measurement intended for characterizing the time-domain specifications, e.g., the rise/fall time of modern high-speed communication transceivers. To reduce hardware overhead, the proposed BIST technique uses the coherent under-sampling principle, and measures implicitly the time interval in a two-pass manner. Simulation results are shown to validate the proposed technique.