IEEE Spectrum
Automated AC (Timing) Characterization for Digital Circuit Testing
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
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ITC '00 Proceedings of the 2000 IEEE International Test Conference
An On-Chip Short-Time Interval Measurement Technique for Testing High-Speed Communication Links
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Towards a Standard for Embedded Core Test: An Example
ITC '99 Proceedings of the 1999 IEEE International Test Conference
BIST for Phase-Locked Loops in Digital Applications
ITC '99 Proceedings of the 1999 IEEE International Test Conference
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A built-in parametric measurement circuit is proposed for time-interval measurement and setup/hold timemeasurement.The main idea is based on the dual-slopetechnique.The minimum resolution is set by resistorarray configuration,which is 1/16 clock period in thispaper and easily extendable to desired precision.Theimperfectness,including the offset voltage and thesettling time,is considered to improve the accuracy.Moreover a simple calibration method is proposed toreduce the measuring error.Experiments on the SRAMaccess time measurement and the register setup/holdtime measurement show the practicality of the proposedunit.