Statistical analysis of extreme values
Statistical analysis of extreme values
Jitter Testing for Gigabit Serial Communication Transceivers
IEEE Design & Test
A New Method for Jitter Decomposition Through Its Distribution Tail Fitting
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A jitter characterization system using a component-invariant vernier delay line
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Jitter Models for the Design and Test of Gbps-Speed Serial Interconnects
IEEE Design & Test
On-Chip Digital Jitter Measurement, from Megahertz to Gigahertz
IEEE Design & Test
Implementation of an Economic Jitter Compliance Test for a Multi-Gigabit Device on ATE
ITC '04 Proceedings of the International Test Conference on International Test Conference
An Accurate Jitter Estimation Technique for Efficient High Speed I/O Testing
ATS '07 Proceedings of the 16th Asian Test Symposium
Jitter, noise, and signal integrity at high-speed
Jitter, noise, and signal integrity at high-speed
Jitter Decomposition in High-Speed Communication Systems
ETS '08 Proceedings of the 2008 13th European Test Symposium
A Jitter Characterizing BIST with Pulse-Amplifying Technique
ATS '09 Proceedings of the 2009 Asian Test Symposium
A 2.5-GHz built-in jitter measurement system in a serial-link transceiver
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Timing jitter is a major limiting factor for data throughput in serial high-speed interfaces, which forces an accurate analysis of the impact on system performance. Histogram-based methods have been developed for this purpose, and can directly relate collected jitter distributions with the bit-error rate (BER). However, real measurements suffer from limitations introduced by the hardware, such as limited sample size, a discrete number of bins or process variations. In this paper we investigate the performance of a widely used, powerful class of fitting methods, when used together with built-in jitter measurements (BIJM). We derive equations to specify minimum requirements for sample size and time resolution, and provide empirical relations to estimate the error statistics for typical test distributions. This allows designers to characterize key parameters of a BIJM design, and to find an optimum trade-off between hardware expense and system accuracy. A typical design example is also provided and validity of the empirical equations demonstrated with experimental jitter measurements. The equations can be used as tools for configuring a BIJM system, and to assist in realizing production tests and on-chip diagnostics.