Boundary Scan for 5-GHz RF Pins Using LC Isolation Networks
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
On-Chip Digital Jitter Measurement, from Megahertz to Gigahertz
IEEE Design & Test
On-Chip Testing Techniques for RF Wireless Transceivers
IEEE Design & Test
RF Testing on a Mixed Signal Tester
Journal of Electronic Testing: Theory and Applications
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Built-in loopback test for IC RF transceivers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A test and calibration strategy for adjustable RF circuits
Analog Integrated Circuits and Signal Processing
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Today's low cost wireless phones have driven a need to be able to economically test high volumes of complex RF IC's at a fraction of the cost of the IC. In June of 2001 the IBM test development group developed a strategy and design to test complex wireless phone front end components for a fraction of the cost of using traditional ATE or rack and stack test solutions. In this paper the architecture of the system is described as well as some of the design, maintenance and implementation considerations. The system is designed to bring the cost of complex manufacturing test of RF IC's equivalent to that of testing discrete components such as resistors or capacitors. Given the drastic reduction of test cost and the relative ease of implementation of this solution this architecture sets the bar for future RF test solutions. To the best of our knowledge, this architecture has resulted in the fastest RF tester in the world.