Detection and Evaluation of Deterministic Jitter Causes in CP-PLL's Due to Macro Level Faults and Pre-Detection Using Simple Methods

Authors:
Martin John Burbidge
Affiliations:
Centre for Microsystems Engineering, Lancaster University, UK
Venue:
Journal of Electronic Testing: Theory and Applications
Year:
2005

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Abstract

This paper presents an analog built-in testing (BIT) architecture and its implementation. It enables the frequency response and harmonic distortion characterizations of an integrated device-under-test (DUT) through a digital off-chip interface. External ...