Modeling and minimization of PMOS NBTI effect for robust nanometer design
Proceedings of the 43rd annual Design Automation Conference
An analytical model for negative bias temperature instability
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Adaptive techniques for overcoming performance degradation due to aging in digital circuits
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Circuit techniques for dynamic variation tolerance
Proceedings of the 46th Annual Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Circuit-level NBTI macro-models for collaborative reliability monitoring
Proceedings of the 20th symposium on Great lakes symposium on VLSI
SRAM-based NBTI/PBTI sensor system design
Proceedings of the 47th Design Automation Conference
NBTI-aware DVFS: a new approach to saving energy and increasing processor lifetime
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Optimized self-tuning for circuit aging
Proceedings of the Conference on Design, Automation and Test in Europe
An on-chip NBTI sensor for measuring pMOS threshold voltage degradation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Adaptive techniques for overcoming performance degradation due to aging in CMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Tracking on-chip age using distributed, embedded sensors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Compact degradation sensors for monitoring NBTI and oxide degradation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Methods for fault tolerance in networks-on-chip
ACM Computing Surveys (CSUR)
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Negative Bias Temperature Instability (NBTI) is one of the most critical device reliability issues facing scaled CMOS technology. In order to better understand the characteristics of this mechanism, accurate and efficient means of measuring its effects must be explored. In this work, we describe an on-chip NBTI degradation sensor using two delay-locked loops (DLL). The increase in PMOS transistor threshold due to NBTI stress is translated into the control voltage of a DLL for high sensing gain. Measurements from a 0.13μm test chip show a maximum gain of 16X in the operating range of interest, with microsecond order measurement times for minimal unwanted recovery. The proposed NBTI sensor also supports various DC and AC stress modes.