Positive bias temperature instability in nMOSFETs with ultra-thin Hf-silicate gate dielectrics
Microelectronic Engineering - Proceedings of the 14th biennial conference on insulating films on semiconductors
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Modeling and minimization of PMOS NBTI effect for robust nanometer design
Proceedings of the 43rd annual Design Automation Conference
An analytical model for negative bias temperature instability
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
NBTI-aware synthesis of digital circuits
Proceedings of the 44th annual Design Automation Conference
An on-chip NBTI sensor for measuring PMOS threshold voltage degradation
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Body bias voltage computations for process and temperature compensation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Variation-aware supply voltage assignment for minimizing circuit degradation and leakage
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
NBTI-Aware Clustered Power Gating
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimized self-tuning for circuit aging
Proceedings of the Conference on Design, Automation and Test in Europe
Minimizing leakage power in aging-bounded high-level synthesis with design time multi-Vth assignment
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Impact of positive bias temperature instability (PBTI) on 3T1D-DRAM cells
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Leakage power and circuit aging cooptimization by gate replacement techniques
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
In-field aging measurement and calibration for power-performance optimization
Proceedings of the 48th Design Automation Conference
Impact of NBTI on performance of domino logic circuits in nano-scale CMOS
Microelectronics Journal
Efficient selection and analysis of critical-reliability paths and gates
Proceedings of the great lakes symposium on VLSI
Impact of positive bias temperature instability (PBTI) on 3T1D-DRAM cells
Integration, the VLSI Journal
Row-based FBB: A design-time optimization for post-silicon tunable circuits
Microelectronics Journal
Circuit reliability: from physics to architectures
Proceedings of the International Conference on Computer-Aided Design
Reliable on-chip systems in the nano-era: lessons learnt and future trends
Proceedings of the 50th Annual Design Automation Conference
Virtually-aged sampling DMR: unifying circuit failure prediction and circuit failure detection
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 0.00 |
Negative Bias Temperature Instability (NBTI) in PMOS transistors has become a major reliability concern in present-day digital circuit design. Further, with the recent usage of Hf-based high-k dielectrics for gate leakage reduction, Positive Bias Temperature Instability (PBTI), the dual effect in NMOS transistors has also reached significant levels. Consequently, designers are required to build in substantial guard-bands into their designs, leading to large area and power overheads, in order to guarantee reliable operation over the lifetime of a chip. We propose a guard-banding technique based on adaptive body bias (ABB) and adaptive supply voltage (ASV), to recover the performance of an aged circuit, and compare its merits over previous approaches.