Distributed sleep transistor network for power reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Enabling fine-grain leakage management by voltage anchor insertion
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Modeling and minimization of PMOS NBTI effect for robust nanometer design
Proceedings of the 43rd annual Design Automation Conference
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology
Proceedings of the 17th ACM Great Lakes symposium on VLSI
An analytical model for negative bias temperature instability
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Temperature-aware NBTI modeling and the impact of input vector control on performance degradation
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
The impact of NBTI on the performance of combinational and sequential circuits
Proceedings of the 44th annual Design Automation Conference
NBTI-aware synthesis of digital circuits
Proceedings of the 44th annual Design Automation Conference
Timing-driven row-based power gating
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Invited paper: Network-on-Chip design and synthesis outlook
Integration, the VLSI Journal
Node Criticality Computation for Circuit Timing Analysis and Optimization under NBTI Effect
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Adaptive techniques for overcoming performance degradation due to aging in digital circuits
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
On the efficacy of input Vector Control to mitigate NBTI effects and leakage power
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Gate replacement techniques for simultaneous leakage and aging optimization
Proceedings of the Conference on Design, Automation and Test in Europe
Design and optimization of multithreshold CMOS (MTCMOS) circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Charge Recycling in Power-Gated CMOS Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
NBTI effects on tree-like clock distribution networks
Proceedings of the great lakes symposium on VLSI
Circuit reliability: from physics to architectures
Proceedings of the International Conference on Computer-Aided Design
Employing circadian rhythms to enhance power and reliability
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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The emergence of Negative Bias Temperature Instability (NBTI) as the most relevant source of reliability in sub-90nm technologies has led to a new facet of the traditional trade-off between power and reliability. NBTI effects in fact manifest themselves as an increase of the propagation delay of the devices over time, which adds up to the delay penalty incurred by most low-power design solutions. This implies that, given a desired lifetime of a circuit (i.e., a given performance target at some point in time), a power-managed component will fail earlier than a nonpower-managed one. In this work, we show how it is possible to partially overcome this conflict, by leveraging the benefits in terms of aging provided by power-gating (i.e., by using switches that disconnect a logic block from the ground). Thanks to some electrical properties, it is possible to nullify aging effects during standby periods. Based on this important property, we propose a methodology for a NBTI-aware power gating that allows synthesizing low-leakage circuits with maximum lifetime.