Using soft-edge flip-flops to compensate NBTI-induced delay degradation
Proceedings of the 19th ACM Great Lakes symposium on VLSI
NBTI-aware sleep transistor design for reliable power-gating
Proceedings of the 19th ACM Great Lakes symposium on VLSI
NBTI-aware power gating for concurrent leakage and aging optimization
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Statistical reliability analysis under process variation and aging effects
Proceedings of the 46th Annual Design Automation Conference
NBTI-Aware Clustered Power Gating
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reliability- and process variation-aware placement for FPGAs
Proceedings of the Conference on Design, Automation and Test in Europe
TG-based technique for NBTI degradation and leakage optimization
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Impact of adaptive voltage scaling on aging-aware signoff
Proceedings of the Conference on Design, Automation and Test in Europe
Reliability improvement of logic and clock paths in power-efficient designs
ACM Journal on Emerging Technologies in Computing Systems (JETC) - Special Issue on Reliability and Device Degradation in Emerging Technologies and Special Issue on WoSAR 2011
Critical-reliability path identification and delay analysis
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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For sub-65nm technology nodes, Negative Bias Temperature Instability (NBTI) has become a primary limiting factor of circuit lifetime. During the past few years, researchers have spent considerable and continuous efforts on modeling and characterization of NBTI-caused delay degradation at different design levels. Searching for solutions which can effectively reduce NBTI impact on circuit delay is still under way. In this work, we use node criticality computation to drive NBTI aware timing analysis and optimization. Circuits after being applied this optimization flow show strong resistance to NBTI delaydegradation. Particularly, for the first time, we propose node criticality computation algorithm under the NBTI aware timing analysis and optimization framework and give answers to the following questions which have not been answered yet. They are: (1) how to define node criticality in a circuit under NBTI effect; (2) how to find the critical nodes which once are protected NBTI timing degradation will be effectively reduced. Experimental results show that by protecting the critical nodes found by this framework, circuit delay degradation can be reduced by up to 50%.