Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Proceedings of the 42nd annual Design Automation Conference
Asymptotic probability extraction for non-normal distributions of circuit performance
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Criticality computation in parameterized statistical timing
Proceedings of the 43rd annual Design Automation Conference
A framework for statistical timing analysis using non-linear delay and slew models
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
An analytical model for negative bias temperature instability
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Process Variation and NBTI Tolerant Standard Cells to Improve Parametric Yield and Lifetime of ICs
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
The impact of NBTI on the performance of combinational and sequential circuits
Proceedings of the 44th annual Design Automation Conference
NBTI-aware synthesis of digital circuits
Proceedings of the 44th annual Design Automation Conference
Clustering based pruning for statistical criticality computation under process variations
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
An efficient method to identify critical gates under circuit aging
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Node Criticality Computation for Circuit Timing Analysis and Optimization under NBTI Effect
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Modeling of NBTI-Induced PMOS Degradation under Arbitrary Dynamic Temperature Variation
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
NBTI-aware power gating design
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Integration, the VLSI Journal
Enabling system-level modeling of variation-induced faults in networks-on-chips
Proceedings of the 48th Design Automation Conference
On the Simulation of HCI-Induced Variations of IC Timings at High Level
Journal of Electronic Testing: Theory and Applications
Instruction-set extension under process variation and aging effects
Proceedings of the Conference on Design, Automation and Test in Europe
Runtime power estimator calibration for high-performance microprocessors
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Use it or lose it: wear-out and lifetime in future chip multiprocessors
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
Novel crack sensor for TSV-based 3D integrated circuits: design and deployment perspectives
Proceedings of the International Conference on Computer-Aided Design
Eagle-eye: a near-optimal statistical framework for noise sensor placement
Proceedings of the International Conference on Computer-Aided Design
Critical-reliability path identification and delay analysis
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Circuit reliability is affected by various fabrication-time and run-time effects. Fabrication-induced process variation has significant impact on circuit performance and reliability. Various aging effects, such as negative bias temperature instability, cause continuous performance and reliability degradation during circuit run-time usage. In this work, we present a statistical analysis framework that characterizes the lifetime reliability of nanometer-scale integrated circuits by jointly considering the impact of fabrication-induced process variation and run-time aging effects. More specifically, our work focuses on characterizing circuit threshold voltage lifetime variation and its impact on circuit timing due to process variation and the negative bias temperature instability effect, a primary aging effect in nanometer-scale integrated circuits. The proposed work is capable of characterizing the overall circuit lifetime reliability, as well as efficiently quantifying the vulnerabilities of individual circuit elements. This analysis framework has been carefully validated and integrated into an iterative design flow for circuit lifetime reliability analysis and optimization.