Statistical reliability analysis under process variation and aging effects
Proceedings of the 46th Annual Design Automation Conference
Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC
Proceedings of the International Conference on Computer-Aided Design
Benchmarking for research in power delivery networks of three-dimensional integrated circuits
Proceedings of the 2013 ACM international symposium on International symposium on physical design
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The CTE mismatch-induced stress in 3D ICs may initiate cracks from the interface between a TSV and its dielectric liner, and propagates them on the silicon substrate surface. If a crack grows beyond the keep-out-zone (KOZ) of a TSV, it will jeopardize the reliability of the devices along its propagation path. While such threat can be eliminated by a sufficiently large KOZ, significant area overhead will be incurred. Given the low probability of crack occurrence, we argue that a much more economical approach is to keep KOZ small and filter out bad chips with cracks growing beyond the KOZ during testing. However, traditional microscope or X-ray diffraction based crack detection techniques are cost-prohibitive for massive productions. To address this issue, this paper proposes a novel crack sensor design with very little design or testing overhead. It is simply formed by doping the area surrounding a suspicious TSV. By measuring its DC resistances during testing, cracks that grow beyond the doped area can be easily detected. In addition, through empirical studies on crack dynamics in various TSV configurations, we provide deployment guidelines to minimize the number of sensors needed. To the best of our knowledge, this is the first work to propose a macro-scale crack detection technique.