Benchmarking for research in power delivery networks of three-dimensional integrated circuits

Authors:
Pei-Wen Luo;Chun Zhang;Yung-Tai Chang;Liang-Chia Cheng;Hung-Hsie Lee;Bih-Lan Sheu;Yu-Shih Su;Ding-Ming Kwai;Yiyu Shi
Affiliations:
Industrial Technology Research Institute, Hsin-Chu, Taiwan Roc;Missouri University of Science and Technology, Rolla, MO, USA;Industrial Technology Research Institute, Hsin-Chu, Taiwan Roc;Industrial Technology Research Institute, Hsin-Chu, Taiwan Roc;Industrial Technology Research Institute, Hsin-Chu, Taiwan Roc;Industrial Technology Research Institute, Hsin-Chu, Taiwan Roc;Industrial Technology Research Institute, Hsin-Chu, Taiwan Roc;Industrial Technology Research Institute, Hsin-Chu, Taiwan Roc;Missouri University of Science and Technology, Rolla, MO, USA
Venue:
Proceedings of the 2013 ACM international symposium on International symposium on physical design
Year:
2013

Citing 9
Cited 1

Simultaneous power and thermal integrity driven via stapling in 3D ICs

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Power grid analysis benchmarks

Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Optimizing Decoupling Capacitors in 3D Circuits for Power Grid Integrity

IEEE Design & Test
2011 TAU power grid simulation contest: benchmark suite and results

Proceedings of the International Conference on Computer-Aided Design
Fast static analysis of power grids: algorithms and implementations

Proceedings of the International Conference on Computer-Aided Design
On the preconditioner of conjugate gradient method: a power grid simulation perspective

Proceedings of the International Conference on Computer-Aided Design
PGT_SOLVER: an efficient solver for power grid transient analysis

Proceedings of the International Conference on Computer-Aided Design
PowerRush: efficient transient simulation for power grid analysis

Proceedings of the International Conference on Computer-Aided Design
Parallel forward and back substitution for efficient power grid simulation

Proceedings of the International Conference on Computer-Aided Design

Novel crack sensor for TSV-based 3D integrated circuits: design and deployment perspectives

Proceedings of the International Conference on Computer-Aided Design

Quantified Score

Hi-index	0.00

Visualization

Abstract

Power integrity is generally considered to be one of the major bottlenecks hindering the prevalence of three-dimensional integrated circuits (3D ICs). The higher integration density and smaller footprint result in significantly increased power density, which threatens the system reliability. In view of this, there has been groundswell of interest in academia to model, design or optimize the power delivery networks (PDNs) in 3D ICs. Unfortunately, while several PDN benchmarks exist for 2D PDNs, none is available in the context of 3D. As a consequence, most existing literature resorts to ad-hoc designs by artificially stacking 2D PDNs for experiments, rendering the results less convincing. In this paper, we put forward a set of ten PDN benchmarks that are extracted from industrial 3D designs. These designs are carefully selected such that they cover a wide range of functionality, size, TSV number, tier number and packaging style. We hope that the released benchmarks can facilitate and promote research in 3D PDNs.