Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Circuit optimization using statistical static timing analysis
Proceedings of the 42nd annual Design Automation Conference
Gate sizing using incremental parameterized statistical timing analysis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Modeling and minimization of PMOS NBTI effect for robust nanometer design
Proceedings of the 43rd annual Design Automation Conference
Circuit Failure Prediction and Its Application to Transistor Aging
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
The impact of NBTI on the performance of combinational and sequential circuits
Proceedings of the 44th annual Design Automation Conference
NBTI-aware synthesis of digital circuits
Proceedings of the 44th annual Design Automation Conference
Probabilistic Treatment of General Combinational Networks
IEEE Transactions on Computers
An efficient method to identify critical gates under circuit aging
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
Statistical reliability analysis under process variation and aging effects
Proceedings of the 46th Annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Instruction-set extension under process variation and aging effects
Proceedings of the Conference on Design, Automation and Test in Europe
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Aging effect degrades circuit performance in the runtime, interacts with fabrication-induced device parameter variation, and thus posing significant impact on circuit lifetime reliability. In this work, a statistical circuit optimization flow is proposed to ensure lifetime reliability of the manufactured chip in the presence of process variation and aging effects. It exploits a variation-aware gate-level statistical aging degradation model to characterize circuit lifetime reliability, identifies a set of worst duty cycles on the inputs of statistically critical gates to estimate the worst delay degradations on these gates. Based on the delay degradation information, statistical gate sizing is performed which enables the manufactured chip to satisfy lifetime reliability constraint in term of low area overhead.