Improved Techniques for Estimating Signal Probabilities
IEEE Transactions on Computers
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Electronics beyond nano-scale CMOS
Proceedings of the 43rd annual Design Automation Conference
Modeling and minimization of PMOS NBTI effect for robust nanometer design
Proceedings of the 43rd annual Design Automation Conference
An analytical model for negative bias temperature instability
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Circuit Failure Prediction and Its Application to Transistor Aging
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
The impact of NBTI on the performance of combinational and sequential circuits
Proceedings of the 44th annual Design Automation Conference
Thermal-aware reliability analysis for platform FPGAs
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A framework for estimating NBTI degradation of microarchitectural components
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
NBTI tolerant microarchitecture design in the presence of process variation
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Statistical reliability analysis under process variation and aging effects
Proceedings of the 46th Annual Design Automation Conference
International Journal of Parallel Programming
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Circuit-level NBTI macro-models for collaborative reliability monitoring
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Joint logic restructuring and pin reordering against NBTI-induced performance degradation
Proceedings of the Conference on Design, Automation and Test in Europe
A linear programming approach for minimum NBTI vector selection
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Analyzing throughput of power and thermal-constraint multicore processor under NBTI effect
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Integration, the VLSI Journal
TG-based technique for NBTI degradation and leakage optimization
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Analysis and mitigation of NBTI-induced performance degradation for power-gated circuits
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Failure diagnosis of asymmetric aging under NBTI
Proceedings of the International Conference on Computer-Aided Design
In-system and on-the-fly clock tuning mechanism to combat lifetime performance degradation
Proceedings of the International Conference on Computer-Aided Design
Efficient selection and analysis of critical-reliability paths and gates
Proceedings of the great lakes symposium on VLSI
Physics matters: statistical aging prediction under trapping/detrapping
Proceedings of the 49th Annual Design Automation Conference
Static NBTI Reduction Using Internal Node Control
ACM Transactions on Design Automation of Electronic Systems (TODAES)
M-IVC: Applying multiple input vectors to co-optimize aging and leakage
Microelectronics Journal
Proactive aging management in heterogeneous NoCs through a criticality-driven routing approach
Proceedings of the Conference on Design, Automation and Test in Europe
Aging-aware compiler-directed VLIW assignment for GPGPU architectures
Proceedings of the 50th Annual Design Automation Conference
Process Variations-Aware Statistical Analysis Framework for Aging Sensors Insertion
Journal of Electronic Testing: Theory and Applications
ARGO: aging-aware GPGPU register file allocation
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
Proceedings of the International Conference on Computer-Aided Design
Critical-reliability path identification and delay analysis
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Negative Bias Temperature Instability (NBTI) is the leading factor of circuit performance degradation. Due to its complex dependence on operating conditions, especially signal probability, it is a tremendous challenge to accurately predict the degradation rate in reality. On the other hand, we demonstrate in this work that it is feasible to reliably predict the relative importance of gates under NBTI. By identifying critical gates that are the most important ones for timing degradation, we will be able to effectively protect the circuit from aging, with the minimum design overhead. The proposed method is based on a new timing analysis framework that integrates a NBTI-aware library. For each potential critical path, we prove that there exists a particular signal probability, which leads to the worst case of timing degradation. The search of such worst case signal probability provides a safe guardband for the degradation, yet avoiding overly pessimistic analysis. By applying this method to ISCAS and ITC benchmark circuits at the 65nm node, we demonstrate that in average only 1% of total gates need to be protected in order to control the timing degradation within 10% in ten years. Since this method only requires one-time analysis of each critical path, it is very efficient in computation. With the information of critical gates available, it further enables other resilient design techniques to mitigate circuit aging under NBTI.