NBTI-aware synthesis of digital circuits
Proceedings of the 44th annual Design Automation Conference
An efficient method to identify critical gates under circuit aging
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Characterizing chip-multiprocessor variability-tolerance
Proceedings of the 45th annual Design Automation Conference
Amdahl's Law in the Multicore Era
Computer
A framework for estimating NBTI degradation of microarchitectural components
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Proceedings of the 46th Annual Design Automation Conference
Joint logic restructuring and pin reordering against NBTI-induced performance degradation
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
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NBTI (Negative Bias Temperature Instability) which can degrade the switching speed of PMOS transistors has become a major reliability challenge. In this paper, we investigate the throughput impact of NBTI on power and thermal-constraint multicore processors and show up to 30% degradation when both process variation and NBIT are considered. Then we evaluate the effectiveness of core rotation, adaptive voltage scaling and adaptive body biasing to improve the throughput of power and thermal constrained multicore processors. Our experimental results demonstrate 11.1% improvement in VDD is sufficient to guarantee throughput after 10-yr NBTI influence when processor variation is not considered. In contract, ABB technique is not able to recover throughput loss caused by NBTI.