GLACIER: A Hot Carrier Gate Level Circuit Characterization and Simulation System for VLSI Design
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Efficient and accurate gate sizing with piecewise convex delay models
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Modeling and minimization of PMOS NBTI effect for robust nanometer design
Proceedings of the 43rd annual Design Automation Conference
An analytical model for negative bias temperature instability
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
The impact of NBTI on the performance of combinational and sequential circuits
Proceedings of the 44th annual Design Automation Conference
NBTI-aware synthesis of digital circuits
Proceedings of the 44th annual Design Automation Conference
An efficient method to identify critical gates under circuit aging
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Built-In Proactive Tuning System for Circuit Aging Resilience
DFT '08 Proceedings of the 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems
Adaptive techniques for overcoming performance degradation due to aging in digital circuits
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Optimized self-tuning for circuit aging
Proceedings of the Conference on Design, Automation and Test in Europe
Representative critical reliability paths for low-cost and accurate on-chip aging evaluation
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the International Conference on Computer-Aided Design
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Aging effects such as negative bias temperature instability (NBTI) and hot carrier injection (HCI) have become major concerns when designing reliable circuits at sub-45nm technologies. It is vital to efficiently identify the paths that age at a faster rate than others in the field. Moreover, gates having the most impact on the degradation of these paths must be identified for compensation purposes. In this paper, we propose (i) a new timing analysis flow, which can quickly and accurately predict path and gate degradation due to NBTI and HCI effects, and (ii) a novel algorithm that can effectively identify the smallest set of critical-reliability gates while quantitatively evaluates their relative importance to path delay degradation. This facilitates reliability-enhancement methods to efficiently mitigate reliability threats using minimum area overhead. Our simulation results on several benchmark circuits demonstrate the efficiency of the proposed technique.