Layout-driven hot-carrier degradation minimization using logic restructuring techniques
Proceedings of the 38th annual Design Automation Conference
Timing modeling of flipflops considering aging effects
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Aging analysis at gate and macro cell level
Proceedings of the International Conference on Computer-Aided Design
Efficient selection and analysis of critical-reliability paths and gates
Proceedings of the great lakes symposium on VLSI
Critical-reliability path identification and delay analysis
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Gate level circuit simulation on hot carrier degradation is introduced for the first time by the GLACIER system presented in this paper. The inherent advantages such as high speed and high capacity of the gate level simulation as compared to the traditional transistor level hot carrier simulation makes the design-in reliability simulation possible and practical for the deep submicron VLSI circuit designs with millions of transistors. By virtue of a unique ratio based modeling technique, GLACIER system provides a very high accuracy, which is mostly within 1% difference of transistor level hot carrier simulation.