GLACIER: A Hot Carrier Gate Level Circuit Characterization and Simulation System for VLSI Design
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
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Proceedings of the 44th annual Design Automation Conference
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Node Criticality Computation for Circuit Timing Analysis and Optimization under NBTI Effect
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ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Statistical reliability analysis under process variation and aging effects
Proceedings of the 46th Annual Design Automation Conference
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Circuit reliability analysis at the presilicon stage has become vital for sub-45nm technology designs in particular, due to aging effects, such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI). To avoid potential reliability hazards in the postsilicon stage, current large-scale designs for commercial implementation overpessimistically analyze circuit aging under assumed worst-case workload in order not to violate the corner cases even for low possibilities, thus introducing unnecessary margin in the design timing analysis. The major issue is lack of an effective aging analysis method applicable to large designs with low CPU runtime, which is mainly due to: (1) conventional reliability tools are extremely time-consuming for circuit-level timing analysis and thus are not practical for large designs; (2) mathematical models developed to expedite the process are not accurate due to the high complexity of aging effects. In this article, a comprehensive analysis is presented to highlight the importance of each aging parameter. Then, a novel methodology is developed based on current commercial reliability tools to guarantee its high accuracy on circuit-level aging analysis. Existing proven low-level mathematical models are further enhanced to extensively speed up a higher level analysis by taking advantage of the explicit intermediate conditions stored in a pregenerated lookup table. Our results indicate ≥244X improved computational efficiency, ≤5% relative error, and ≤0.7% absolute error compared with commercial reliability analysis tools (e.g., HSPICE MOSRA).