ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Temperature-aware NBTI modeling and the impact of input vector control on performance degradation
Proceedings of the conference on Design, automation and test in Europe
Interactive presentation: Pulse propagation for the detection of small delay defects
Proceedings of the conference on Design, automation and test in Europe
The impact of NBTI on the performance of combinational and sequential circuits
Proceedings of the 44th annual Design Automation Conference
NBTI-aware synthesis of digital circuits
Proceedings of the 44th annual Design Automation Conference
An efficient method to identify critical gates under circuit aging
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
NBTI resilient circuits using adaptive body biasing
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Bounded-lifetime integrated circuits
Proceedings of the 45th annual Design Automation Conference
Adaptive techniques for overcoming performance degradation due to aging in digital circuits
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A framework for estimating NBTI degradation of microarchitectural components
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
NBTI-aware power gating for concurrent leakage and aging optimization
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Testing resistive opens and bridging faults through pulse propagation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
International Journal of Parallel Programming
The impact of NBTI effect on combinational circuit: modeling, simulation, and analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
NBTI-Aware Clustered Power Gating
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Programmable aging sensor for automotive safety-critical applications
Proceedings of the Conference on Design, Automation and Test in Europe
Joint logic restructuring and pin reordering against NBTI-induced performance degradation
Proceedings of the Conference on Design, Automation and Test in Europe
Gate replacement techniques for simultaneous leakage and aging optimization
Proceedings of the Conference on Design, Automation and Test in Europe
Process-variation resilient and voltage scalable DCT architecture for robust low-power computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Integration, the VLSI Journal
Adaptive techniques for overcoming performance degradation due to aging in CMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leakage power and circuit aging cooptimization by gate replacement techniques
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis and mitigation of NBTI-induced performance degradation for power-gated circuits
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Impact of NBTI on performance of domino logic circuits in nano-scale CMOS
Microelectronics Journal
Delay sensing for long-term variations and defects monitoring in safety---critical applications
Analog Integrated Circuits and Signal Processing
In-system and on-the-fly clock tuning mechanism to combat lifetime performance degradation
Proceedings of the International Conference on Computer-Aided Design
Aging analysis at gate and macro cell level
Proceedings of the International Conference on Computer-Aided Design
Efficient selection and analysis of critical-reliability paths and gates
Proceedings of the great lakes symposium on VLSI
Early prediction of NBTI effects using RTL source code analysis
Proceedings of the 49th Annual Design Automation Conference
A novel gate-level NBTI delay degradation model with stacking effect
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Variation-aware supply voltage assignment for simultaneous power and aging optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
NBTI-aware circuit node criticality computation
ACM Journal on Emerging Technologies in Computing Systems (JETC)
ACM Journal on Emerging Technologies in Computing Systems (JETC) - Special Issue on Reliability and Device Degradation in Emerging Technologies and Special Issue on WoSAR 2011
Critical-reliability path identification and delay analysis
ACM Journal on Emerging Technologies in Computing Systems (JETC)
| Hi-index | 0.00 |
Negative Bias Temperature Instability (NBTI) has become one of the major causes for temporal reliability degradation of nanoscale circuits. In this paper, we analyze the temporal delay degradation of logic circuits due to NBTI. We show that knowing the threshold voltage degradation of a single transistor due to NBTI, one can predict the performance degradation of a circuit with a reasonable degree of accuracy. We also propose a sizing algorithm taking NBTI-affected performance degradation into account to ensure the reliability of nanoscale circuits for a given period of time. Experimental results on several benchmark circuits show that with an average of 8.7% increase in area one can ensure reliable performance of circuits for 10 years.