Efficient algorithms for extracting the K most critical paths in timing analysis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Modeling and minimization of PMOS NBTI effect for robust nanometer design
Proceedings of the 43rd annual Design Automation Conference
The impact of NBTI on the performance of combinational and sequential circuits
Proceedings of the 44th annual Design Automation Conference
NBTI-aware synthesis of digital circuits
Proceedings of the 44th annual Design Automation Conference
Adaptive techniques for overcoming performance degradation due to aging in digital circuits
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Scheduled voltage scaling for increasing lifetime in the presence of NBTI
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Semiconductor Device Modeling with Spice
Semiconductor Device Modeling with Spice
NBTI-aware power gating for concurrent leakage and aging optimization
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
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As the technology scales, the increase of circuit delay over time due to NBTI (negative bias temperature instability) effect is not negligible any more. It has been known that voltage scaling is an effective scheme that is able to mitigate the NBTI effect. However, a careful control of voltage scaling is required not to increase the dissipation of dynamic power significantly. On the other hand, body biasing can also be used to mitigate the NBTI effect by lowering down the threshold voltage, but its effectiveness is limited, as will be demonstrated in this work, and it increases the leakage power. This work addresses an important problem of minimizing the power consumption of circuit while controlling the NBTI induced delay increase to meet the circuit timing constraint by simultaneously utilizing the effects of voltage scaling and body biasing on both NBTI and power consumption. Precisely, we solve the problem of finding a set of supply and body biasing voltage values to apply circuit clusters on standard cell based design to minimize the total power consumption while satisfying the constraint of circuit life time, considering the NBTI induced delay factor in circuit timing computation. By a comprehensive analysis on the relations between the values of supply and body biasing voltages and the values of the resulting power consumption and NBTI induced delay, we precisely formulate the problem, and transform it into a problem of convex optimization to solve it efficiently. Through extensive experimentation using ISCAS benchmark designs, it is shown that the proposed approach to the simultaneous exploitation of supply voltage and body biasing is able to produce designs with 14% and 8% reduced energy consumption on average over the designs produced by the design time NBTI-aware guard-banding based voltage scaling [20] and the run time NBTI-aware voltage scaling [4], respectively.