ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
Exploiting Structural Duplication for Lifetime Reliability Enhancement
Proceedings of the 32nd annual international symposium on Computer Architecture
Modeling and minimization of PMOS NBTI effect for robust nanometer design
Proceedings of the 43rd annual Design Automation Conference
A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Variation-aware supply voltage assignment for minimizing circuit degradation and leakage
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Aging effects of leakage optimizations for caches
Proceedings of the 20th symposium on Great lakes symposium on VLSI
NBTI-aware DVFS: a new approach to saving energy and increasing processor lifetime
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Dynamic indexing: concurrent leakage and aging optimization for caches
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Optimized self-tuning for circuit aging
Proceedings of the Conference on Design, Automation and Test in Europe
Minimizing leakage power in aging-bounded high-level synthesis with design time multi-Vth assignment
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Buffering of frequent accesses for reduced cache aging
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Leakage power and circuit aging cooptimization by gate replacement techniques
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Impact of NBTI on performance of domino logic circuits in nano-scale CMOS
Microelectronics Journal
Energy-optimal caches with guaranteed lifetime
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Circuit reliability: from physics to architectures
Proceedings of the International Conference on Computer-Aided Design
Impact of adaptive voltage scaling on aging-aware signoff
Proceedings of the Conference on Design, Automation and Test in Europe
Energy-optimal SRAM supply voltage scheduling under lifetime and error constraints
Proceedings of the 50th Annual Design Automation Conference
VAWOM: temperature and process variation aware wearout management in 3D multicore architecture
Proceedings of the 50th Annual Design Automation Conference
Tracking on-chip age using distributed, embedded sensors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Variation-aware supply voltage assignment for simultaneous power and aging optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Employing circadian rhythms to enhance power and reliability
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Application-specific memory partitioning for joint energy and lifetime optimization
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 0.00 |
Negative Bias Temperature Instability (NBTI) is a leading reliability concern for integrated circuits (ICs). It gradually increases the threshold voltages of PMOS transistors, thereby increasing delay. We propose scheduled voltage scaling, a technique that gradually increases the operating voltage of the IC to compensate for NBTI-related performance degradation. Scheduled voltage scaling has the potential to increase IC lifetime by 46% relative to the conventional approach using guard banding for ICs fabricated using a 45nm process.