A Model of Workloads and its Use in Miss-Rate Prediction for Fully Associative Caches
IEEE Transactions on Computers
Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Reducing leakage in a high-performance deep-submicron instruction cache
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Drowsy caches: simple techniques for reducing leakage power
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Impact of NBTI on SRAM Read Stability and Design for Reliability
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Cache miss behavior: is it √2?
Proceedings of the 3rd conference on Computing frontiers
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Scheduled voltage scaling for increasing lifetime in the presence of NBTI
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
NBTI-aware power gating for concurrent leakage and aging optimization
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Dynamic indexing: concurrent leakage and aging optimization for caches
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Recovery Boosting: A Technique to Enhance NBTI Recovery in SRAM Arrays
ISVLSI '10 Proceedings of the 2010 IEEE Annual Symposium on VLSI
Investigating the impact of NBTI on different power saving cache strategies
Proceedings of the Conference on Design, Automation and Test in Europe
ARGO: aging-aware GPGPU register file allocation
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
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This work addresses the aging of the memory sub-system due to NBTI (Negative Bias Temperature Instability) in systems that have to provide a guaranteed level of service, and specifically, a guaranteed lifetime. Our approach leverages a novel cache architecture in which a smart joint use of redundancy and power management allows us to obtain caches that meet a desired lifetime target with minimal energy consumption. This is made possible by exploiting the possibility of putting the cache sub-block used for redundancy into a deep low-power state, thus allowing more energy saving than a regular architecture. Sacrificing a portion of the cache for aging mitigation only marginally affects performance thanks to the non-linear dependency of miss rate versus cache size, which allows to find the best cache size that maximizes the objective. Simulation results show that it is possible to meet the target lifetime by achieving energy reductions (measured over the lifetime of the system) ranging from 3X to 10X (2X to 8X) for a lifetime target of 15 (25) years, with marginal miss rate overhead.