Performance tradeoffs in cache design
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Characteristics of performance-optimal multi-level cache hierarchies
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Synthetic Traces for Trace-Driven Simulation of Cache Memories
IEEE Transactions on Computers
A Model of Workloads and its Use in Miss-Rate Prediction for Fully Associative Caches
IEEE Transactions on Computers
Performance Analysis of Cache Memories
Journal of the ACM (JACM)
ACM Computing Surveys (CSUR)
A simple linear model of demand paging performance
Communications of the ACM
Efficient Analytical Modelling of Multi-Level Set-Associative Caches
HPCN Europe '99 Proceedings of the 7th International Conference on High-Performance Computing and Networking
Optimum Power/Performance Pipeline Depth
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
The next resource war: computation vs. communication
Proceedings of the 2008 international workshop on System level interconnect prediction
Fractal communication in software data dependency graphs
Proceedings of the twentieth annual symposium on Parallelism in algorithms and architectures
A dollar from 15 cents: cross-platform management for internet services
ATC'08 USENIX 2008 Annual Technical Conference on Annual Technical Conference
Static Cache Partitioning Robustness Analysis for Embedded On-Chip Multi-processors
Transactions on High-Performance Embedded Architectures and Compilers I
Is 3D chip technology the next growth engine for performance improvement?
IBM Journal of Research and Development
Moguls: a model to explore the memory hierarchy for bandwidth improvements
Proceedings of the 38th annual international symposium on Computer architecture
Toward five-dimensional scaling: how density improves efficiency in future computers
IBM Journal of Research and Development
CPU DB: recording microprocessor history
Communications of the ACM
CPU DB: Recording Microprocessor History
Queue - Processors
Implications of electronics technology trends to algorithm design
VoCS'08 Proceedings of the 2008 international conference on Visions of Computer Science: BCS International Academic Conference
Energy-optimal caches with guaranteed lifetime
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
Amdahl's law in the era of process variation
International Journal of High Performance Systems Architecture
Computer performance analysis and the Pi Theorem
Computer Science - Research and Development
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It has long been empirically observed that the cache miss rate decreased as a power law of cache size, where the power was approximately -1/2. In this paper, we examine the dependence of the cache miss rate on cache size both theoretically and through simulation. By combining the observed time dependence of the cache reference pattern with a statistical treatment of cache entry replacement, we predict that the cache miss rate should vary with cache size as an inverse power law for a first level cache. The exponent in the power law is directly related to the time dependence of cache references, and lies between -0.3 to -0.7. Results are presented for both direct mapped and set associative caches, and for various levels of the cache hierarchy. Our results demonstrate that the dependence of cache miss rate on cache size arises from the temporal dependence of the cache access pattern.