Static Cache Partitioning Robustness Analysis for Embedded On-Chip Multi-processors

  • Authors:

  • Anca M. Molnos;Sorin D. Cotofana;Marc J. Heijligers;Jos T. Eijndhoven

  • Affiliations:

  • NXP Semiconductors, HTC 31, Eindhoven, The Netherlands;Technical University of Delft, Mekelweg 4, Delft, The Netherlands;NXP Semiconductors, HTC 31, Eindhoven, The Netherlands;NXP Semiconductors, HTC 31, Eindhoven, The Netherlands

  • Venue:
  • Transactions on High-Performance Embedded Architectures and Compilers I
  • Year:
  • 2007

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Abstract

In this paper we propose a method to analyze the robustness of multi-tasking media applications when mapped on an on-chip multiprocessor platform. We assume a multiprocessor structure which embeds a cache hierarchy with two levels: an L1 that each processor may have and an L2 shared among the processors. To enable compositionality, i.e, to be able to evaluate the system performance out of the individual tasks performance, this shared L2 is partitioned per task basis. In this paper we first introduce two metrics to quantify the robustness. The internal robustness is estimated by a sensitivity function which measures the performance variations induced by the inter-task cache interference. The external robustness is quantified by a stability function which reflects the variations induced by different input data on the partitioned L2 behavior. Subsequently, we exercise our method on a set of multimedia applications running on a CAKE multi-processor platform. Our experiments indicate that, if the cache is partitioned, the sensitivity is on average 4%. whereas for the shared cache it is 25%. Over the investigated workloads the stability is at least 90% therefore, for the those applications, we can conclude that the static cache partitioning is quite robust to input stimuli.