Characteristics of performance-optimal multi-level cache hierarchies

  • Authors:

  • S. Przybylski;M. Horowitz;J. Hennessy

  • Affiliations:

  • Computer Systems Laboratory, Stanford University, Stanford University, CA;Computer Systems Laboratory, Stanford University, Stanford University, CA;Computer Systems Laboratory, Stanford University, Stanford University, CA

  • Venue:
  • ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
  • Year:
  • 1989

Quantified Score

Hi-index 0.01

Visualization

Abstract

The increasing speed of new generation processors will exacerbate the already large difference between CPU cycle times and main memory access times. As this difference grows, it will be increasingly difficult to build single-level caches that are both fast enough to match these fast cycle times and large enough to effectively hide the slow main memory access times. One solution to this problem is to use a multi-level cache hierarchy. This paper examines the relationship between cache organization and program execution time for multi-level caches. We show that a first-level cache dramatically reduces the number of references seen by a second-level cache, without having a large effect on the number of second-level cache misses. This reduction in the number of second-level cache hits changes the optimal design point by decreasing the importance of the cycle-time of the second-level cache relative to its size. The lower the first-level cache miss rate, the less important the second-level cycle time becomes. This change in relative importance of cycle time and miss rate makes associativity more attractive and increases the optimal cache size for second-level caches over what they would be for an equivalent single-level cache system.