A simulation study of two-level caches
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Performance tradeoffs in cache design
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Characteristics of performance-optimal multi-level cache hierarchies
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Evaluating Associativity in CPU Caches
IEEE Transactions on Computers
Simulation and analysis of a pipeline processor
WSC '89 Proceedings of the 21st conference on Winter simulation
Cache and memory hierarchy design: a performance-directed approach
Cache and memory hierarchy design: a performance-directed approach
i486 microprocessor programmer's reference manual
i486 microprocessor programmer's reference manual
Simulation of queueing models in computer systems
Queueing theory and applications
Performance simulation analysis of RISC-based multiprocessors under uniform and nonuniform traffic
Information Sciences: an International Journal
Analyzing multiple register sets
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
High-Performance Computer Architecture
High-Performance Computer Architecture
ACM SIGARCH Computer Architecture News
ACM SIGARCH Computer Architecture News
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This paper presents a simulation methodology for evaluating the performance of CISC computers. The method is called Message Flow Technique (MFT). MFT has several advantages over Instruction Flow Technique (IFT) we presented in [1]. The proposed methodology is applied to a single and two-level cache CISC system using 80486 SX as a case study. It was found that with a single-level on-chip cache of size 8K, the performance of the system is considerably limited by the service time of BIU(Bus Interface Unit). The average service time of BIU, per instruction, was found to be around 1.0135 microseconds for our Modified Gibson Mix (MGM). With a second-level external cache of sizes 16K, 32K, 64K, and 128K the average performance improvements were found to be 1.4%, 18.6%, 39% and 53% respectively. The methodology presented here is an efficient and easy to use tool that could help performance analysts in evaluating computer systems.