Simulation and analysis of a pipeline processor

Authors:
P. G. Emma;J. W. Knight;J. H. Pomerence;T. R. Puzak;R. N. Rechtschaffen
Affiliations:
-;-;-;-;-
Venue:
WSC '89 Proceedings of the 21st conference on Winter simulation
Year:
1989

Citing 0
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Abstract

In this paper we describe a software simulator (a timer) that is used to model a wide range of pipeline processors. A set of performance equations is developed that allow a user to separate the performance of a processor into its infinite-cache and finite-cache performance values. We then use the timer to study the performance of two different machine organizations. Performance curves are presented that help a user compare the performance of each organization (in terms of MIPS and cycles per instruction) to the cycle time chosen to implement the design.