Co-optimization of memory access and task scheduling on MPSoC architectures with multi-level memory

Authors:
Yi He;Chun Jason Xue;Cathy Qun Xu;Edwin H.-M. Sha
Affiliations:
University of Texas at Dallas, Richardson, TX;City University of Hong Kong, Kowloon, Hong Kong;University of Texas at Dallas, Richardson, TX;University of Texas at Dallas, Richardson, TX
Venue:
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Year:
2010

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Abstract

An MPSoC system usually consists of a number of processors, a memory hierarchy and a communication mechanism between processors. Because of the gap between the constantly increasing processor speed and slower memory access, how to utilize the memory subsystem more efficiently has become a critical issue for improving the overall system performance. To address this problem, two algorithms are proposed in this paper. The first one uses the integer linear programming method so that the memory access cost is minimized while tasks are scheduled in as short a time as possible. The second one is a heuristic algorithm which can achieve close to optimum results with linear running time. The experimental results show that the memory access cost can be reduced up to 56% comparing to LIST scheduling.