Benchmarking and comparison of the task graph scheduling algorithms
Journal of Parallel and Distributed Computing
On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An optimal memory allocation for application-specific multiprocessor system-on-chip
Proceedings of the 14th international symposium on Systems synthesis
Storage allocation for embedded processors
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
Exploiting shared scratch pad memory space in embedded multiprocessor systems
Proceedings of the 39th annual Design Automation Conference
Memory Issues in Embedded Systems-on-Chip: Optimizations and Exploration
Memory Issues in Embedded Systems-on-Chip: Optimizations and Exploration
An optimal memory allocation scheme for scratch-pad-based embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Hardware-Software partitioning and pipelined scheduling of transformative applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hypertool: A Programming Aid for Message-Passing Systems
IEEE Transactions on Parallel and Distributed Systems
Scratchpad memory: design alternative for cache on-chip memory in embedded systems
Proceedings of the tenth international symposium on Hardware/software codesign
Assigning Program and Data Objects to Scratchpad for Energy Reduction
Proceedings of the conference on Design, automation and test in Europe
Polynomial-time algorithm for on-chip scratchpad memory partitioning
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Power Efficient Processor Architecture and The Cell Processor
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Partitioning and Pipelined Scheduling of Embedded System Using Integer Linear Programming
ICPADS '05 Proceedings of the 11th International Conference on Parallel and Distributed Systems - Workshops - Volume 02
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
Customized on-chip memories for embedded chip multiprocessors
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Heap data allocation to scratch-pad memory in embedded systems
Journal of Embedded Computing - Cache exploitation in embedded systems
Allocation and scheduling for MPSoCs via decomposition and no-good generation
IJCAI'05 Proceedings of the 19th international joint conference on Artificial intelligence
Data locality enhancement for CMPs
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Software-directed combined cpu/link voltage scaling fornoc-based cmps
SIGMETRICS '08 Proceedings of the 2008 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Scratchpad allocation for concurrent embedded software
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
A Framework for Task Scheduling and Memory Partitioning for Multi-Processor System-on-Chip
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
Towards embedded runtime system level optimization for MPSoCs: on-chip task allocation
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Cache-aware scheduling and analysis for multicores
EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software
Dynamic thread and data mapping for NoC based CMPs
Proceedings of the 46th Annual Design Automation Conference
Hardware/software partitioning and pipelined scheduling on runtime reconfigurable FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Variable Partitioning and Scheduling for MPSoC with Virtually Shared Scratch Pad Memory
Journal of Signal Processing Systems
Scratchpad allocation for concurrent embedded software
ACM Transactions on Programming Languages and Systems (TOPLAS)
Pipelined data parallel task mapping/scheduling technique for MPSoC
Proceedings of the Conference on Design, Automation and Test in Europe
An MILP-based performance analysis technique for non-preemptive multitasking MPSoC
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
Co-optimization of memory access and task scheduling on MPSoC architectures with multi-level memory
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Compiler-directed memory management for heterogeneous MPSoCs
Journal of Systems Architecture: the EUROMICRO Journal
Dynamic and adaptive SPM management for a multi-task environment
Journal of Systems Architecture: the EUROMICRO Journal
Algorithms for optimally arranging multicore memory structures
EURASIP Journal on Embedded Systems
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Static bus schedule aware scratchpad allocation in multiprocessors
Proceedings of the 2011 SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
EURASIP Journal on Embedded Systems
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Joint task assignment and cache partitioning with cache locking for WCET minimization on MPSoC
Journal of Parallel and Distributed Computing
Optimizing latency and throughput of application workflows on clusters
Parallel Computing
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Neighborhood-aware data locality optimization for NoC-based multicores
CGO '11 Proceedings of the 9th Annual IEEE/ACM International Symposium on Code Generation and Optimization
Processor energy characterization for compiler-assisted software energy reduction
Journal of Electrical and Computer Engineering
FCC-SDP: a fast close-coupled shared data pool for multi-core DSPs
ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
MultiMaKe: Chip-multiprocessor driven memory-aware kernel pipelining
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
Write activity reduction on non-volatile main memories for embedded chip multiprocessors
ACM Transactions on Embedded Computing Systems (TECS)
A survey of pipelined workflow scheduling: Models and algorithms
ACM Computing Surveys (CSUR)
Minimizing accumulative memory load cost on multi-core DSPs with multi-level memory
Journal of Systems Architecture: the EUROMICRO Journal
Embedded RAIDs-on-chip for bus-based chip-multiprocessors
ACM Transactions on Embedded Computing Systems (TECS)
Journal of Systems Architecture: the EUROMICRO Journal
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Multiprocessor system-on-chip (MPSoC) is an integrated circuit containing multiple instruction-set processors on a single chip that implements most of the functionality of a complex electronic system. An MPSoC architecture is, in general, customized for an embedded application. A critical component of this customization process is the on-chip memory system configuration. Embedded systems increasingly employ software-controlled scratchpad memory(SPM) due to its inherent advantages in terms of area, energy, and timing predictability compared to caches. An application-specific flexible partitioning of the on-chip SPM budget among the processors is critical for performance optimization. Moreover, scheduling the tasks of an application on to the processors and partitioning the SPM are inter-dependent even though these steps are decoupled in the traditional design space exploration process. In this work, we design an integrated task mapping, scheduling, SPM partitioning, and data allocation technique based on Integer Linear Programming(ILP)formulation. Our ILP formulation explores the optimal performance limit and shows that integrated task schedul-ing and SPM optimization improves performance by up to 80% for embedded applications.