Schedulability analysis of heterogeneous systems for performance message sequence chart
Proceedings of the 6th international workshop on Hardware/software codesign
Performance Estimation for Real-Time Distributed Embedded Systems
IEEE Transactions on Parallel and Distributed Systems
Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment
Journal of the ACM (JACM)
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Holistic scheduling and analysis of mixed time/event-triggered distributed embedded systems
Proceedings of the tenth international symposium on Hardware/software codesign
Schedulability Analysis for Tasks with Static and Dynamic Offsets
RTSS '98 Proceedings of the IEEE Real-Time Systems Symposium
The Non-preemptive Scheduling of Periodic Tasks upon Multiprocessors
Real-Time Systems
Integrated scratchpad memory optimization and task scheduling for MPSoC architectures
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Performance estimation of distributed real-time embedded systems by discrete event simulations
EMSOFT '07 Proceedings of the 7th ACM & IEEE international conference on Embedded software
New Schedulability Test Conditions for Non-preemptive Scheduling on Multiprocessor Platforms
RTSS '08 Proceedings of the 2008 Real-Time Systems Symposium
Allocation and scheduling for MPSoCs via decomposition and no-good generation
IJCAI'05 Proceedings of the 19th international joint conference on Artificial intelligence
Robust non-preemptive hard real-time scheduling for clustered multicore platforms
Proceedings of the Conference on Design, Automation and Test in Europe
Schedulability analysis for systems with data and control dependencies
Euromicro-RTS'00 Proceedings of the 12th Euromicro conference on Real-time systems
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For real-time applications, it is necessary to estimate the worst-case performance early in the design process without actual hardware implementation. While the non-preemptive task scheduling is pertinent to multi-core platforms because of easy implementation and high performance, its scheduling anomaly behavior makes the worst-case performance estimation extremely difficult. In this paper, we propose an analysis technique based on mixed integer linear programming (MILP) to estimate the worstcase performance of each task in a non-preemptive multitask application on multi-processor system-on-chip architecture. MILP provides a systematic way to describe the complex interaction among task scheduling, communication architecture, and task execution, which affects the worst-case behavior dynamically. The proposed analysis technique overcomes several limitations that previous work usually has; it allows multiple tasks with different periods and models contention on the communication architecture. We show that the proposed analysis takes affordable computation time to make it of practical value even though it has exponential complexity in theory. The proposed technique estimates a safe bound on task latency statistically, which is demonstrated by extensive random simulations.