Integrated scratchpad memory optimization and task scheduling for MPSoC architectures
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Synthesis of heterogeneous pipelined multiprocessor systems using ILP: jpeg case study
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
A design flow for application specific heterogeneous pipelined multiprocessor systems
Proceedings of the 46th Annual Design Automation Conference
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-power adaptive pipelined MPSoCs for multimedia: an H.264 video encoder case study
Proceedings of the 48th Design Automation Conference
Robust Software Partitioning with Multiple Instantiation
INFORMS Journal on Computing
ICA3PP'12 Proceedings of the 12th international conference on Algorithms and Architectures for Parallel Processing - Volume Part I
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In this paper, an integer linear programming (ILP) based approach is proposed for integrated hardware/software (HW/SW) partitioning and pipelined scheduling of embedded systems for multimedia applications. The ILP approach not only partitions and maps each computation task of a particular multimedia application onto a component of the heterogeneous multiprocessor architecture, but also schedules and pipelines the execution of these computation tasks while considering communication time. The objective is to minimize the total component cost and the number of pipeline stages subject to the throughput constraint on the pipelined architecture. Experiments on two real multimedia applications are used to demonstrate the effectiveness of the proposed approach.