Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Thermal-Aware Task Allocation and Scheduling for Embedded Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Thermal-Aware Floorplanning Using Genetic Algorithms
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Combinatorial Auction-Based Protocols for Resource Allocation in Grids
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 13 - Volume 14
Integrated scratchpad memory optimization and task scheduling for MPSoC architectures
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Carbon: architectural support for fine-grained parallelism on chip multiprocessors
Proceedings of the 34th annual international symposium on Computer architecture
Core fusion: accommodating software diversity in chip multiprocessors
Proceedings of the 34th annual international symposium on Computer architecture
Temperature aware task scheduling in MPSoCs
Proceedings of the conference on Design, automation and test in Europe
Thousand core chips: a technology perspective
Proceedings of the 44th annual Design Automation Conference
Temperature-aware processor frequency assignment for MPSoCs using convex optimization
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Proceedings of the conference on Design, automation and test in Europe
User-aware dynamic task allocation in networks-on-chip
Proceedings of the conference on Design, automation and test in Europe
Dynamic task allocation strategies in MPSoC for soft real-time applications
Proceedings of the conference on Design, automation and test in Europe
A Novel System-Level On-Chip Resource Allocation Method for Manycore Architectures
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
Communication-aware heuristics for run-time task mapping on NoC-based MPSoC platforms
Journal of Systems Architecture: the EUROMICRO Journal
EURASIP Journal on Embedded Systems
Mapping on multi/many-core systems: survey of current and emerging trends
Proceedings of the 50th Annual Design Automation Conference
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Next generation multiprocessor systems-on-chip (MPSoCs) are expected to contain numerous processing elements, interconnected via on-chip networks, executing real-time applications. It is anticipated that runtime optimization algorithms which dynamically adjust system parameters with the purpose of optimizing the system's operation, will be embedded in the system software and/or hardware. In this paper, we present a methodology for simulating and evaluating system-level optimization algorithms, demonstrated by the case of on-chip dynamic task allocation applied to generic MPSoC architectures. Through this methodology, we are able to show that dynamic, system-level bidding-based task allocation can improve system performance, when compared to a round robin allocation, in popular MPSoC applications.