IEEE Transactions on Computers
IEEE Transactions on Parallel and Distributed Systems
Loop Transformations for Fault Detection in Regular Loops on Massively Parallel Systems
IEEE Transactions on Parallel and Distributed Systems
Proceedings of the 6th international workshop on Hardware/software codesign
Performance of image and video processing with general-purpose processors and media ISA extensions
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
Low-Cost Task Scheduling for Distributed-Memory Machines
IEEE Transactions on Parallel and Distributed Systems
Viper: A Multiprocessor SOC for Advanced Set-Top Box and Digital TV Systems
IEEE Design & Test
An Effective Processor Allocation Strategy for Multiprogrammed Shared-Memory Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
Failure detection algorithms for a reliable execution of parallel programs
SRDS '95 Proceedings of the 14TH Symposium on Reliable Distributed Systems
(R) FAST: A Low-Complexity Algorithm for Efficient Scheduling of DAGs on Parallel Processors
ICPP '96 Proceedings of the Proceedings of the 1996 International Conference on Parallel Processing - Volume 2
The future of multiprocessor systems-on-chips
Proceedings of the 41st annual Design Automation Conference
Efficient Feasibility Analysis for Real-Time Systems with EDF Scheduling
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Scheduler implementation in MP SoC design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Hardware and software cache prefetching techniques for MPEG benchmarks
IEEE Transactions on Circuits and Systems for Video Technology
Proceedings of the Conference on Design, Automation and Test in Europe
A task remapping technique for reliable multi-core embedded systems
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Co-optimization of memory access and task scheduling on MPSoC architectures with multi-level memory
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Analysis and optimization of fault-tolerant task scheduling on multiprocessor embedded systems
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Minimizing accumulative memory load cost on multi-core DSPs with multi-level memory
Journal of Systems Architecture: the EUROMICRO Journal
Energy-aware task mapping and scheduling for reliable embedded computing systems
ACM Transactions on Embedded Computing Systems (TECS) - Special Section ESFH'12, ESTIMedia'11 and Regular Papers
Failure-Aware Task Scheduling of Synchronous Data Flow Graphs Under Real-Time Constraints
Journal of Signal Processing Systems
Communication and migration energy aware task mapping for reliable multiprocessor systems
Future Generation Computer Systems
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Advances in semiconductor technologies have placed MPSoCs center stage as a standard architecture for embedded applications of ever increasing complexity. Because of real-time constraints, applications are usually statically parallelized and scheduled onto the target MPSoC so as to obtain predictable worst-case performance. However, both technology scaling trends and resource competition among applications have led to variations in the availability of resources during execution, thus questioning the dynamic viability of the initial static schedules. To eliminate this problem, in this paper we propose to statically generate a compact schedule with predictable response to various resource availability constraints. Such schedules are generated by adhering to a novel band structure, capable of spawning dynamically a regular reassignment upon resource variations. Through incorporating several soft constraints into the original scheduling heuristic, the proposed technique can furthermore exploit the inherent timing slack between dependent tasks, thus retaining the spatial and temporal locality of the original schedule. The efficacy of the proposed technique is confirmed by incorporating it into a widely adopted list scheduling heuristic, and experimentally verifying it in the context of single processor deallocations.