Impact of NBTI on SRAM Read Stability and Design for Reliability
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
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WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
Scheduled voltage scaling for increasing lifetime in the presence of NBTI
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
NBTI-aware power gating for concurrent leakage and aging optimization
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
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Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Dynamic indexing: concurrent leakage and aging optimization for caches
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Recovery Boosting: A Technique to Enhance NBTI Recovery in SRAM Arrays
ISVLSI '10 Proceedings of the 2010 IEEE Annual Symposium on VLSI
Investigating the impact of NBTI on different power saving cache strategies
Proceedings of the Conference on Design, Automation and Test in Europe
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Impact of Negative-Bias Temperature Instability in Nanoscale SRAM Array: Modeling and Analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This work addresses the energy efficiency of the memory architecture in safety-critical systems that have to guarantee a given level of service and a minimum lifetime. We specifically target SRAM structures in which decreased reliability manifests itself in terms of the aging induced by NBTI (Negative Bias Temperature Instability), and in which the level of service is represented by the bit-error rate (BER). Our approach is based on the idea of determining an energy-optimal scheduling of supply voltages for the SRAM that satisfy the specified lifetime and BER constraints. The construction of the scheduling leverages semi-empirical models for the quantity of interest (aging, energy, memory performance, error rate) in terms of the supply voltage, and is determined through a search-based algorithm in the corresponding solution space. The optimization framework is embedded into a design space exploration tool that allows browsing the energy/performance/reliability space for the various desired lifetime/error rate and by varying architectural parameters such operating frequency and memory size.