Proceedings of the 44th annual Design Automation Conference
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
NBTI tolerant microarchitecture design in the presence of process variation
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Aging effects of leakage optimizations for caches
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Reliability analysis of power gated SRAM under combined effects of NBTI and PBTI in nano-scale CMOS
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Proactive NBTI mitigation for busy functional units in out-of-order microprocessors
Proceedings of the Conference on Design, Automation and Test in Europe
Impact of positive bias temperature instability (PBTI) on 3T1D-DRAM cells
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Buffering of frequent accesses for reduced cache aging
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Impact of positive bias temperature instability (PBTI) on 3T1D-DRAM cells
Integration, the VLSI Journal
NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems
Journal of Electronic Testing: Theory and Applications
Current Consumption and Power Integrity of CMOS Digital Circuits Under NBTI Wearout
Journal of Electronic Testing: Theory and Applications
Design and implementation of an adaptive proactive reconfiguration technique for SRAM caches
Proceedings of the Conference on Design, Automation and Test in Europe
Energy-optimal SRAM supply voltage scheduling under lifetime and error constraints
Proceedings of the 50th Annual Design Automation Conference
ARGO: aging-aware GPGPU register file allocation
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
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One of the major reliability concerns in nanoscale very large-scale integration design is the time-dependent negative- bias-temperature-instability (NBTI) degradation. Due to the higher operating temperature and increasing vertical oxide field, threshold voltage (Vt) of PMOS transistors can increase with time under NBTI. In this paper, we examine the impact of NBTI degradation in memory elements of digital circuits, focusing on the conventional 6T-SRAM-array topology. An analytical expression for the time-dependent Vt degradation in PMOS transistors based on the empirical reaction-diffusion (RD) framework was employed for our analysis. Using the RD-based Vt model, we analytically examine the impact of NBTI degradation in critical performance parameters of SRAM array. These parameters include the following: (1) static noise margin; (2) statistical READ and WRITE stability; (3) parametric yield; and (4) standby leakage current (IDDQ). We show that due to NBTI, READ stability of SRAM cell degrades, while write stability and standby leakage improve with time. Furthermore, by carefully examining the degradation in leakage current due to NBTI, it is possible to characterize and predict the lifetime behavior of NBTI degradation in real circuit operation.