Variation-aware supply voltage assignment for minimizing circuit degradation and leakage

Authors:
Xiaoming Chen;Yu Wang;Yu Cao;Yuchun Ma;Huazhong Yang
Affiliations:
Dept. of E.E., TNList, Tsinghua University, Beijing, China;Dept. of E.E., TNList, Tsinghua University, Beijing, China;Dept. of E.E., Arizona State University, Tempe, USA;Dept. of C.S., TNList, Tsinghua University, Beijing, China;Dept. of E.E., TNList, Tsinghua University, Beijing, China
Venue:
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Year:
2009

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Abstract

As technology scales, Negative Bias Temperature Instability (NBTI) has become a major reliability concern for circuit designers. And the growing process variations can no longer be ignored. Meanwhile, reducing leakage power remains to be one of the design goals. In this paper, we first present a platform for NBTI-aware statistical timing and leakage power analysis. A variation-aware supply voltage assignment (SVA) technique combining dual Vdd assignment and dynamic Vdd scaling techniques is proposed to minimize NBTI degradation and leakage. Based on the statistical platform, we analyze the impact of Vth variations on NBTI degradation and leakage. The experimental results show that our SVA technique can mitigate on average 52.98% of NBTI degradation with little or without leakage power increase; furthermore, it can reduce on average 32.46% more leakage power compared with the pure single Vdd scaling technique. Compared with scheduled voltage scaling technique [9], our dynamic scaling technique is more effective because the circuit delay will exactly meet the specification at each dynamically decided time node during circuit operation.