Variation-aware supply voltage assignment for simultaneous power and aging optimization

Authors:
Xiaoming Chen;Yu Wang;Yu Cao;Yuchun Ma;Huazhong Yang
Affiliations:
Department of Electronic Engineering, Tsinghua National Laboratory for Information Science and Technology, Tsinghua University, Beijing, China;Department of Electronic Engineering, Tsinghua National Laboratory for Information Science and Technology, Tsinghua University, Beijing, China;Department of Electrical Engineering, Arizona State University, Tempe, AZ;Department of Computer Science, Tsinghua National Laboratory for Information Science and Technology, Tsinghua University, Beijing, China;Department of Electronic Engineering, Tsinghua National Laboratory for Information Science and Technology, Tsinghua University, Beijing, China
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2012

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Abstract

As technology scales, negative bias temperature instability (NBTI) has become a major reliability concern for circuit designers. And the growing process variations can no longer be ignored. Meanwhile, reducing power consumption remains to be one of the design goals. In this paper, a variation-aware supply voltage assignment (SVA) technique combining dual Vdd assignment and dynamic Vdd scaling is proposed on a statistical platform, to minimize circuit power under an aging-aware timing constraint. The experimental results show that our SVA technique can mitigate on average 62% of the NBTI-induced circuit delay degradation. Compared with guard-banding and single Vdd scaling approaches, our approach saves more energy.