Dynamic effects in the detection of bridging faults in CMOS ICs
Journal of Electronic Testing: Theory and Applications
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IEEE Transactions on Computers
Resistance Characterization for Weak Open Defects
IEEE Design & Test
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Proceedings of the 40th annual Design Automation Conference
On the capability of delay tests to detect bridges and opens
ATS '97 Proceedings of the 6th Asian Test Symposium
Testing for Resistive Opens and Stuck Opens
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Resistive Bridge Fault Modeling, Simulation and Test Generation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Defect-Based Delay Testing of Resistive Vias-Contacts A Critical Evaluation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Statistical Timing Analysis using Levelized Covariance Propagation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
On Hazard-free Patterns for Fine-delay Fault Testing
ITC '04 Proceedings of the International Test Conference on International Test Conference
Evaluating the Effectiveness of Detecting Delay Defects in the Slack Interval: A Simulation Study
ITC '04 Proceedings of the International Test Conference on International Test Conference
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Interactive presentation: Pulse propagation for the detection of small delay defects
Proceedings of the conference on Design, automation and test in Europe
A new delay test based on delay defect detection within slack intervals (DDSI)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Experimental Characterization of CMOS Interconnect Open Defects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper addresses the problems related to resistive opens and bridging faults that lie out of the most critical paths. These faults cannot be detected by traditional delay fault testing because the induced delay defects are not large enough to result in timing violations when the test rate is equal to the nominal operating frequency. In spite of this problem, resistive opens and bridgings should be detected because they may give rise to reliability problems. To detect them, we propose a testing method that is based on the propagation of pulses within the faulty circuit and that exploits the degraded capability of faulty paths to propagate pulses. The effectiveness of our method is analyzed at the transistor level and compared with the use of reduced clock periods to detect the same class of faults. Results show similar performance in the case of resistive opens and better performance in the case of bridgings. Moreover, the proposed approach is not affected by possible problems in the clock distribution.