Low Voltage Test in Place of Fast Clock in DDSI Delay Test
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Interactive presentation: Pulse propagation for the detection of small delay defects
Proceedings of the conference on Design, automation and test in Europe
Testing resistive opens and bridging faults through pulse propagation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An on-chip delay measurement technique using signature registers for small-delay defect detection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test compaction for small-delay defects using an effective path selection scheme
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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A new delay testing scheme that identifies abnormal delays in the slack interval by comparing switching delays in neighboring dies on a wafer has been recently proposed and validated on experimental circuits. In this paper we evaluate the effectiveness of this new approach through the simulation of injected delay faults in the ISCAS benchmark circuits. The simulations are performed using a simple switched RC (resistorcapacitor) switching delay model. The results indicate that the new delay testing approach is orders of magnitude more effective in detecting and diagnosing smaller delay defects that increase circuit path delays by 10-50%. The new methodology can address increasing concerns that failure to detect such small delay faults during test may be the cause of significant unreliability in emerging nanometer technologies.