Enhancing test efficiency for delay fault testing using multiple-clocked schemes
Proceedings of the 39th annual Design Automation Conference
Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Bounding Circuit Delay by Testing a Very Small Subset of Paths
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Facilitating Rapid First Silicon Debug
ITC '02 Proceedings of the 2002 IEEE International Test Conference
On-chip delay measurement for silicon debug
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
On Hazard-free Patterns for Fine-delay Fault Testing
ITC '04 Proceedings of the International Test Conference on International Test Conference
Evaluating the Effectiveness of Detecting Delay Defects in the Slack Interval: A Simulation Study
ITC '04 Proceedings of the International Test Conference on International Test Conference
An Improved Method for Identifying Linear Dependencies in Path Delay Faults
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Test-Pattern Grading and Pattern Selection for Small-Delay Defects
VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
An All-Digital High-Precision Built-In Delay Time Measurement Circuit
VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
Enhancing Silicon Debug via Periodic Monitoring
DFT '08 Proceedings of the 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems
Diagnosis framework for locating failed segments of path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Path-RO: a novel on-chip critical path delay measurement under process variations
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Nanometer Technology Designs: High-Quality Delay Tests
Nanometer Technology Designs: High-Quality Delay Tests
Automated Selection of Signals to Observe for Efficient Silicon Debug
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
A Low Overhead On-Chip Path Delay Measurement Circuit
ATS '09 Proceedings of the 2009 Asian Test Symposium
A novel faster-than-at-speed transition-delay test method considering IR-drop effects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Correlating system test Fmax with structural test Fmax and process monitoring measurements
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects
DFT '10 Proceedings of the 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems
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This paper presents a delay measurement technique using signature analysis, and a scan design for the proposed delay measurement technique to detect small-delay defects. The proposed measurement technique measures the delay of the explicitly sensitized paths with the resolution of the on-chip variable clock generator. The proposed scan design realizes complete on-chip delay measurement in short measurement time using the proposed delay measurement technique and extra latches for storing the test vectors. The evaluation with Rohm 0.18-µm process shows that the measurement time is 67.8% reduced compared with that of the delay measurement with standard scan design on average. The area overhead is 23.4% larger than that of the delay measurement architecture using standard scan design, and the difference of the area overhead between enhanced scan design and the proposed method is 7.4% on average. The data volume is 2.2 times of that of test set for normal testing on average.