On signal tracing in post-silicon validation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Path criticality computation in parameterized statistical timing analysis
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Simulation-based signal selection for state restoration in silicon debug
Proceedings of the International Conference on Computer-Aided Design
Trace signal selection to enhance timing and logic visibility in post-silicon validation
Proceedings of the International Conference on Computer-Aided Design
X-tracer: a reconfigurable X-tolerant trace compressor for silicon debug
Proceedings of the 49th Annual Design Automation Conference
Formal-analysis-based trace computation for post-silicon debug
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An on-chip delay measurement technique using signature registers for small-delay defect detection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automating data analysis and acquisition setup in a silicon debug environment
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Post-silicon debugging of PMU integration errors using behavioral models
Integration, the VLSI Journal
Post-silicon platform for the functional diagnosis and debug of networks-on-chip
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
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Internal signals of a circuit are observed to analyze, understand, and debug nonconforming chip behavior. The number of signals that can be observed is limited by bandwidth and storage requirements. This paper presents an automated procedure to select which signals to observe to facilitate early detection of circuit malfunction to help find the root cause of a bug. This paper exploits the nature of error propagation in sequential circuits by observing signals which are most often sensitized to possible errors. Given a functional input vector set, an error transmission matrix is generated by analyzing which flip-flops are sensitized to other flip-flops. Signal observability is enhanced by merging data from relatively independent flip-flops. The final set of signals to observe is determined through integer linear programming (ILP) which provides a set of locations that maximally cover the possible error sites within given constraints. Experimental results indicate that the cycle in which a bug first appears can be more rapidly and precisely found with the proposed approach thereby speeding up the post-silicon debug process.