Toward formalizing a validation methodology using simulation coverage
DAC '97 Proceedings of the 34th annual Design Automation Conference
A deductive technique for diagnosis of bridging faults
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Emulation verification of the Motorola 68060
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Modeling the unknown! Towards model-independent fault and error diagnosis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A Survey of Techniques for Formal Verification of Combinational Circuits
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Safety Property Verification Using Sequential SAT and Bounded Model Checking
IEEE Design & Test
Post-verification debugging of hierarchical designs
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Survey of Test Vector Compression Techniques
IEEE Design & Test
Diagnosing Silicon Failures Based on Functional Test Patterns
MTV '06 Proceedings of the Seventh International Workshop on Microprocessor Test and Verification
Abstraction and refinement techniques in automated design debugging
Proceedings of the conference on Design, automation and test in Europe
Trace Compaction using SAT-based Reachability Analysis
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Using unsatisfiable cores to debug multiple design errors
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Proceedings of the conference on Design, automation and test in Europe
BackSpace: formal analysis for post-silicon debug
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Spatial and temporal design debug using partial MaxSAT
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Automated Selection of Signals to Observe for Efficient Silicon Debug
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
Algorithms for state restoration and trace-signal selection for data acquisition in silicon debug
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Trace signal selection for visibility enhancement in post-silicon validation
Proceedings of the Conference on Design, Automation and Test in Europe
On solving the partial MAX-SAT problem
SAT'06 Proceedings of the 9th international conference on Theory and Applications of Satisfiability Testing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Diagnosing arbitrary defects in logic designs using single location at a time (SLAT)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fault diagnosis and logic debugging using Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test pattern generation using Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Defect Modeling Using Fault Tuples
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A hybrid approach for fast and accurate trace signal selection for post-silicon debug
Proceedings of the Conference on Design, Automation and Test in Europe
Leveraging reconfigurability to raise productivity in FPGA functional debug
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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With the growing size of modern designs and more strict time-to-market constraints, design errors can unavoidably escape pre-silicon verification and reside in silicon prototypes. Due to those errors and faults in the fabrication process, silicon debug has become a necessary step in the digital integrated circuit design flow. Embedded hardware blocks, such as scan chains and trace buffers, provide a means to acquire data of internal signals in real time for debugging. However, the amount of the data is limited compared to pre-silicon debugging. This paper presents an automated software solution to analyze this sparse data to detect suspects of the failure in both the spatial and temporal domain. It also introduces a technique to automate the configuration process for trace-buffer-based hardware in order to acquire helpful information for debugging the failure. The technique takes the hardware constraints into account and identifies alternatives for signals not part of the traceable set so that their values can be restored by implications. The experiments demonstrate the effectiveness of the proposed software solution in terms of run-time and resolution.